february 2014 altera corporation ds-1047 datasheet ? 2014 altera corporation. all rights reserved. altera , arria, cyclone, enpirion, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. al l other words and logos identified as tradem arks or service marks are the property o f their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accord ance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liabilit y arising out of the application or use of any information, product, or service desc ribed herein except as expressly agreed to in writing by altera. altera customers a re advised to obtain the latest version of de vice specifications before relying on any published information and before placing or ders for products or services. 101 innovation drive san jose, ca 95134 www.altera.com subscribe iso 9001:2008 registered enpirion power datasheet ey1603 40v, low quiescent current, 150ma linear regulator the altera? enpirion? ey1603 is a wide input voltage range, low quiescent current linear regulator ideally suited for ?always-on? and ?keep alive? applications. the ey1603 operates from an input voltage of +6v to +40v under normal operating conditions and consumes only 18a of quiescent current at no load. the ey1603 has an adjustable output voltage range from 2.5 to 12 v. the ey1603 features an en pin that can be used to put the device into a low-quiescent current shutdown mode where it draws only 2a of supply current. the device features automatic thermal shutdown and current limit protection. the ey1603 is rated over the -40c to +125c temperature range and is av ailable in a 14 lead htssop with an expose d pad package. features ?wide v in range of 6v to 40v ? adjustable output voltage from 2.5v to 12v ? guaranteed 150ma output current ? ultra low 18a typical quiescent current ? low 2a of typical shutdown current ? 1% accurate voltage reference ? low dropout voltage of 295mv at 150ma ? 40v tolerant logic level (ttl/cmos) enable input ? stable operation with 10f output capacitor ?5kv esd hbm rated ? thermal shutdown and current limit protection ? thermally enhanced 14 ld exposed pad htssop package applications ?industrial ? telecommunications table 1. key differences in family of 40v ldo parts part number minimum i out adj or fixed v out ey1602si-adj 50ma adj EY1603TI-ADJ 150ma adj figure 1. typical application figure 2. quiescent current vs temperature (at unity gain). v in = 14v vin vout en vfb gnd c in 0.1f c out 10f r1 r2 v in = 14v v out = 12v epad (gnd) 0 5 10 15 20 25 -50 0 50 100 150 temperature (c) quiescent current (a) 09619 march 14, 2014 rev a
page 2 ey1603 40v, low quiescent current, 150ma linear regulator f ebruary 2014 alte ra corporation ? pin configuration EY1603TI-ADJ (14 ld htssop) top view ordering information part number (notes 1, 2) part marking temp. range (c) enable pin output voltage (v) package (pb-free) pkg. dwg. # EY1603TI-ADJ 1603at -40 to +125 yes adjustable 14 ld htssop m14.173b evb-EY1603TI-ADJ evaluation platform notes: 1. add ?-t*? suffix for tape and reel. 2. these altera enpirion pb-free plastic packaged products empl oy special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination fi nish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). altera en pirion pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requ irements of ipc/jedec j std-020. pin descriptions pin number pin name description 1, 3, 4, 5, 6, 9, 10, 11, 13 nc pins have internal termination and can be left unconnected. connection to ground is optional. 2 vin input voltage pin. a minimum 0.1 f ceramic capacitor is required for pr oper operation. range 6v to 40v. 7 en enable pin. high on this pin enables the device. range 0v to v in . 8 gnd ground pin. 12 vfb this pin is connected to the externa l feedback resistor divider which sets the ldo output voltage. range 0v to 3v. 14 vout regulated output voltage. a 10f ceramic capaci tor is required for stab ility. range 0v to 12v. - epad it is recommended to solder the epad to the ground plane. 1 2 3 4 14 13 12 11 5 6 7 10 9 8 nc vin nc nc nc nc en vout nc vfb nc nc nc gnd thermal pad (gnd) 09619 march 14, 2014 rev a
page 3 ey1603 40v, low quiescent current, 150ma linear regulator february 2014 altera corporation absolute maximum ratings thermal information vin pin to gnd voltage. . . . . . . . . . . . . . . gnd - 0.3v to +45v vout pin to gnd voltage. . . . . . . . . . . . . . .gnd - 0.3v to 16v vfb pin to gnd voltage. . . . . . . . . . . . . . . . . .gnd - 0.3v to 3v en pin to gnd voltage. . . . . . . . . . . . . . . . . gnd - 0.3v to vin output short-circuit duration . . . . . . . . . . . . . . . . . . . indefinite esd rating human body model (tested per jesd22-a114e) . . . . . . 5kv machine model (tested per jesd-a115-a) . . . . . . . . . . 200v charge device model (tested per jesd22-c101c) . . . 2.2kv latch up (tested per jesd78b; class ii, level a). . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 14 ld htssop package (notes 3, 4) 37 5 maximum junction temperature . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . .-65c to +175c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .? recommended operating conditions ambient temperature range . . . . . . . . . . . . . . -40c to +125c vin pin to gnd voltage . . . . . . . . . . . . . . . . . . . . . .+6v to +40v vout pin to gnd voltage . . . . . . . . . . . . . . . . . . +2.5v to +12v en pin to gnd voltage . . . . . . . . . . . . . . . . . . . . . . . . 0v to +40v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposu re to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. ? ja is measured with the component mounted on a high ef fective thermal conductivity test board in free air. 4. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditi ons, unless otherwise noted. v in = 14v, i out = 1ma, c in = 0.1f, c out =10f, t a = t j = -40c to +125c, unless otherwise no ted. typical specifications are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +125c. parameter symbol test conditions min (note 7) typ max (note 7) unit input voltage range v in 64 0 v guaranteed output current i out v in = v out + vdo 150 ma vfb reference voltage v out en = high, v in = 14v, i out = 0.1ma to 150ma 1.211 1.223 1.235 v line regulation ? v out /? v in 3v ? v in ? 40v, i out = 1ma 0.04 0.15 % load regulation ? v out /? i out v in = v out +v do, i out = 100a to 150ma 0.3 0.6 % dropout voltage (note 5) ? v do i out = 1ma, v out = 3.3v 7 33 mv i out = 150ma, v out = 3.3v 380 525 mv i out = 1ma, v out = 5v 7 33 mv i out = 150ma, v out = 5v 295 460 mv shutdown current i shdn en = low 2 3.64 a quiescent current iq en = high, i out = 0ma 18 24 a en = high, i out = 1ma 22 42 a en = high, i out = 10ma 34 60 a en = high, i out = 150ma 90 125 a power supply rejection ratio psrr f = 100hz; v in_ripple = 500mv p-p ; load = 150ma 66 db en function en threshold voltage v en_h v out = off to on 1.485 v v en_l v out = on to off 0.975 v en pin current i en v out = 0v 0.026 a en to regulation time (note 6) t en 1.65 1.93 ms 09619 march 14, 2014 rev a
page 4 ey1603 40v, low quiescent current, 150ma linear regulator f ebruary 2014 alte ra corporation protection features output current limit i limit v out = 0v 175 410 ma thermal shutdown t shdn junction temperature rising +165 c thermal shutdown hysteresis t hyst +20 c notes: 5. dropout voltage is defined as (v in - v out ) when v out is 2% below the value of v out when v in = v out + 3v. 6. enable to regulation is the time the output takes to reach 95% of its final value with v in = 14v and en is taken from v il to v ih in 5ns. for the adjustable versions, the output voltage is set at 5v. 7. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications recommended operating conditi ons, unless otherwise noted. v in = 14v, i out = 1ma, c in = 0.1f, c out =10f, t a = t j = -40c to +125c, unless otherwise no ted. typical specifications are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min (note 7) typ max (note 7) unit 09619 march 14, 2014 rev a
page 5 ey1603 40v, low quiescent current, 150ma linear regulator february 2014 altera corporation typical performance curves v in = 14v, i out = 1ma, v out = 5v, t j = +25c, unless otherwise specified. figure 3. quiescent current vs load current figure 4. quiescent current vs input voltage (no load) figure 5. shutdown current vs temperature (en = 0) figu re 6. output voltage vs te mperature (load = 50ma) 0 20 40 60 80 100 120 05 01 0 01 5 0 load current (ma) -40c +125c +25c quiescent current (a) 0 5 10 15 20 25 30 0 10203040 input voltage (v) -40c +125c +25c quiescent current (a) 0 0.5 1.0 1.5 2.0 2.5 3.0 -50 0 50 100 150 temperature (c) v in = 40v v in = 14v shutdown current (a) -0.010 -0.005 0 0.005 0.010 -50 0 50 100 150 temperature (c) output voltage variation (%) v out = 3.3v v out = 5v 09619 march 14, 2014 rev a
page 6 ey1603 40v, low quiescent current, 150ma linear regulator f ebruary 2014 alte ra corporation figure 7. output voltage vs load current figure 8. start-up waveform figure 9. power supply rejection ratio (l oad = 150ma) figure 10. load transient response typical performance curves v in = 14v, i out = 1ma, v out = 5v, t j = +25c, unless otherwise specified. (continued) 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 0 50 100 150 load current (ma) output voltage (v) +25c +125c -40c time = 500s/div 1v/div 500mv/div en vout 0 10 20 30 40 50 60 70 100 1k 10k 100k 1m frequency (hz) psrr (db) v out = 5v v out = 3.3v 50ma time = 5ms/div 100mv/div 0ma i out v out 09619 march 14, 2014 rev a
page 7 ey1603 40v, low quiescent current, 150ma linear regulator february 2014 altera corporation block diagram reference + soft-start control logic thermal sensor + - ea vin en gnd vout fet driver with current limit vfb 09619 march 14, 2014 rev a
page 8 ey1603 40v, low quiescent current, 150ma linear regulator f ebruary 2014 alte ra corporation functional description functional overview the ey1603 is a high performance, high voltage, low-drop out regulator (ldo) with 150m a sourcing capability. the part is rated to operate over the -40c to +125c temperature ra nge. featuring ultra-low quiesc ent current, it is an ideal choice for ?always-on? applications. it works well under a ?load dump condition? where the input voltage could rise up to 40v. this ldo device also features current limit and thermal shutdown protection. enable control the ey1603 has an enable pin, which turn s the device on when pulled high. when en is low, the ic goes into shutdown mode and draws less than 2a. in ?a lways-on? applications, en can be tied to in. current limit protection the ey1603 has internal current limiting functionality to protect the regulator du ring fault conditio ns. during current limit, the output sources a fixed amount of current largely independent of the outp ut voltage. if the short or overload is removed from v out , the output returns to normal voltage regulation mode. thermal fault protection in the event that the die temperature exceeds a typical value of +165c, the output of the ldo will shut down until the die temperature cools down to a typical +145c. the leve l of power dissipated, combined with the ambient temperature and the thermal impedance of the package, dete rmines if the junction temperature exceeds the thermal shutdown temperature. see the ?power dissip ation? section on page 8 for more details. application information input and output capacitors a minimum 0.1f ceramic capacitor is recommended at the input for proper operation. for the output, a ceramic capacitor with a capacitance of 10f is recommended for the ey1603 to maintain stability. the ground connection of the output capacitor should be routed directly to the gnd pin of the devi ce and also placed close to the ic. output voltage setting the EY1603TI-ADJ output voltage is programmed using an external resistor divide r as shown in figure 11. the output voltage is calculated using equation 1: power dissipation the junction temperature must not exceed the range specif ied in ?recommended operat ing conditions? on page 3. the power dissipation can be calculated using equation 2: the maximum allowable junction temperature, t j(max) and the maximum expected ambient temperature, t a(max) will determine the maximum allowable junction temperature rise ( ? t j ), as shown in equation 2: vin vout en vfb gnd c in 0.1f c out 10f r1 r2 figure 11. output voltage setting v out 1.223v r 1 r 2 ------ - 1 + ?? ?? ?? ? = (eq. 1) ? t j t jmax ?? t amax ?? ? = (eq. 2) 09619 march 14, 2014 rev a
page 9 ey1603 40v, low quiescent current, 150ma linear regulator february 2014 altera corporation to calculate the maximum ambient operating temperatur e, use the junction-to-ambi ent thermal resistance ( ? ja ) as shown in equation 3: board layout recommendations a good pcb layout is important to achieve expected perfor mance. consideration should be taken when placing the components and routing the trace to minimize the ground impedance and keep the parasitic inductance low. the input and output capacitors shou ld have a good ground connection and be pl aced as close to the ic as possible. the feedback trace in the adjustable version should be away from other noisy traces. the 14 ld htssop package uses the copper area on the pcb as a heat-sin k. the epad of this package must be soldered to the copper plane (gnd plane) for effect ive heat dissipation. fi gure 12 shows a curve for ? ja of the package for different copper area sizes. document revision history the table lists the revision history for this document. date version changes february 2014 1.0 initial release. t jmax ?? p dmax ?? x ? ja t a + = (eq. 3) figure 12. ? ja vs epad-mount copper land area on pcb 38 36 34 32 30 28 26 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 epad-mount copper land area on pcb, mm 2 ? ja (c/w) 09619 march 14, 2014 rev a
page 10 ey1603 40v, low quiescent current, 150ma linear regulator f ebruary 2014 alte ra corporation package outline drawing m14.173b 14 lead heat-sink thin shrink small outline package (htssop) rev 1, 1/10 bottom view detail "x" typical recommended land pattern top view b a 1 7 8 14 c plane seating 0.10 c 0.10 c b a h pin #1 i.d. mark 5.00 0.10 4.40 0.10 0.25 +0.05/-0.06 6.40 0.20 c b a 0.05 3.10 0.10 3.00 0.10 0-8 gauge plane see 0.90 +0.15/-0.10 0.60 0.15 0.15 +0.05/-0.06 5 2 3 1 3 1.00 ref 0.65 1.20 max 0.25 0.05 min 0.15 max exposed thermal pad side view detail "x" end view 1. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. 3. dimensions are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m-1994. 5. dimension does not include dambar protrusion. allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm. 6. dimension in ( ) are for reference only. 7. conforms to jedec mo-153, variation abt-1. notes: (1.45) (5.65) (0.65 typ) (0.35 typ) (3.10) (3.00) 09619 march 14, 2014 rev a
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